--VHDL instantiation template

component ecp5_lvds is
    port (LVDS_71_inst_data0: in std_logic_vector(6 downto 0);
        LVDS_71_inst_data1: in std_logic_vector(6 downto 0);
        LVDS_71_inst_data2: in std_logic_vector(6 downto 0);
        LVDS_71_inst_data3: in std_logic_vector(6 downto 0);
        LVDS_71_inst_data4: in std_logic_vector(6 downto 0);
        LVDS_71_inst_data5: in std_logic_vector(6 downto 0);
        LVDS_71_inst_data6: in std_logic_vector(6 downto 0);
        LVDS_71_inst_data7: in std_logic_vector(6 downto 0);
        LVDS_71_inst_dout: out std_logic_vector(7 downto 0);
        LVDS_71_inst_clkout: out std_logic;
        LVDS_71_inst_ready: out std_logic;
        LVDS_71_inst_refclk: in std_logic;
        LVDS_71_inst_sclk: out std_logic;
        LVDS_71_inst_start: in std_logic;
        LVDS_71_inst_sync_clk: in std_logic;
        LVDS_71_inst_sync_reset: in std_logic
    );
    
end component ecp5_lvds; -- sbp_module=true 
_inst: ecp5_lvds port map (LVDS_71_inst_data0 => __,LVDS_71_inst_data1 => __,
            LVDS_71_inst_data2 => __,LVDS_71_inst_data3 => __,LVDS_71_inst_data4 => __,
            LVDS_71_inst_data5 => __,LVDS_71_inst_data6 => __,LVDS_71_inst_data7 => __,
            LVDS_71_inst_dout => __,LVDS_71_inst_clkout => __,LVDS_71_inst_ready => __,
            LVDS_71_inst_refclk => __,LVDS_71_inst_sclk => __,LVDS_71_inst_start => __,
            LVDS_71_inst_sync_clk => __,LVDS_71_inst_sync_reset => __);
